This invention relates to semiconductor devices, and more particularly to methods for manufacturing semiconductor reticles.
Manufacturing of recticles assumes that both the wafer building process and the reticle building process are stable (i.e. the processes do not vary from use-to-use or build-to-build). In reality, no process to manufacture a reticle or a wafer remains consistent. As a result, the critical dimensions of the conductors and semiconductor elements may vary. For printable (wafer level) features, test structures exist that are used to control this variation. No test structures exist, however, for process control using subresolution features where direct control would involve the modification of a process parameter in response to direct measurement of a feature error.
Currently, manufacturers measure the deviation between a feature as drawn in a design and the resulting feature on a semiconductor wafer. If the wafer feature contains dimensional errors, the design is modified. For example, corner serifs are added to modify feature characteristics and this technique is known as an optical proximity correction (OPC) technique. OPC models are constrained to specific reticle manufacturing processes since biasing and feature fidelity are not controlled but assumed stable. With the corrected design, a new reticle is manufactured and then a new wafer is manufactured. This process is iterated until differences between the desired wafer level feature and the actual wafer level feature are acceptable. This iterative process is both time-consuming and expensive.